Design, Automation and Test in Europe (DATE'05) Volume 3 Munich, Germany March 07-March 11 ISBN: 0-7695-2288-2
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.152
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while maintaining 97% of accuracy on average. We also present the development procedure of TLM of a bus architecture.
Citation:
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, "Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture," date, vol. 3, pp.138-139, Design, Automation and Test in Europe (DATE'05) Volume 3, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||