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Design, Automation and Test in Europe (DATE'05) Volume 1
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Munich, Germany
March 07-March 11
ISBN: 0-7695-2288-2
ASCII Text
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G. F. Bouesse, M. Renaudin, S. Dumont, Fabien Germain, "DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 424-429, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.
 
 
BibTex
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@article{ 10.1109/DATE.2005.124,
author = {G. F. Bouesse and M. Renaudin and S. Dumont and Fabien Germain},
title = {DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2005},
issn = {1530-1591},
pages = {424-429},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.124},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
SN - 1530-1591
SP424
EP429
A1 - G. F. Bouesse,
A1 - M. Renaudin,
A1 - S. Dumont,
A1 - Fabien Germain,
PY - 2005
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
G. F. Bouesse, TIMA Laboratory, France
M. Renaudin, TIMA Laboratory, France
S. Dumont, TIMA Laboratory, France
Fabien Germain, SGDN/DCSSI, France
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.
Citation:
G. F. Bouesse, M. Renaudin, S. Dumont, Fabien Germain, "DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement," date, vol. 1, pp.424-429, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005
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