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Design, Automation and Test in Europe (DATE'05) Volume 1
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
Munich, Germany
March 07-March 11
ISBN: 0-7695-2288-2
ASCII Text
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J. L. Rossell?, V. Canals, S. A. Bota, A. Keshavarzi, J. Segura, "A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 206-211, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.
 
 
BibTex
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@article{ 10.1109/DATE.2005.12,
author = {J. L. Rossell? and V. Canals and S. A. Bota and A. Keshavarzi and J. Segura},
title = {A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2005},
issn = {1530-1591},
pages = {206-211},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.12},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
SN - 1530-1591
SP206
EP211
A1 - J. L. Rossell?,
A1 - V. Canals,
A1 - S. A. Bota,
A1 - A. Keshavarzi,
A1 - J. Segura,
PY - 2005
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
J. L. Rossell?, Universitat de les Illes Balears, Spain
V. Canals, Universitat de les Illes Balears, Spain
S. A. Bota, Universitat de les Illes Balears, Spain
A. Keshavarzi, Intel Corp., Portland (OR)
J. Segura, Universitat de les Illes Balears, Spain
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results.
Citation:
J. L. Rossell?, V. Canals, S. A. Bota, A. Keshavarzi, J. Segura, "A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs," date, vol. 1, pp.206-211, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005
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