Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

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	Similar Articles Articles by Yu-Tsun Chien Articles by Dong Chen Articles by Jea-Hong Lou Articles by Gin-Kou Ma Articles by Rob A. Rutenbar Articles by Tamal Mukherjee

Design, Automation and Test in Europe (DATE'05) Volume 1

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters (PDF)

Munich, Germany

March 07-March 11

ISBN: 0-7695-2288-2

	ASCII Text	x
	Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee, "Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 279-280, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005.

	BibTex	x
	@article{ 10.1109/DATE.2005.119, author = {Yu-Tsun Chien and Dong Chen and Jea-Hong Lou and Gin-Kou Ma and Rob A. Rutenbar and Tamal Mukherjee}, title = {Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2005}, issn = {1530-1591}, pages = {279-280}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.119}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters SN - 1530-1591 SP279 EP280 A1 - Yu-Tsun Chien, A1 - Dong Chen, A1 - Jea-Hong Lou, A1 - Gin-Kou Ma, A1 - Rob A. Rutenbar, A1 - Tamal Mukherjee, PY - 2005 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Yu-Tsun Chien, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan

Dong Chen, Carnegie Mellon University, Pittsburgh, Pennsylvania

Jea-Hong Lou, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan

Gin-Kou Ma, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan

Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, Pennsylvania

Tamal Mukherjee, Carnegie Mellon University, Pittsburgh, Pennsylvania

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.119

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 ?m CMOS process.

Citation:

Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee, "Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters," date, vol. 1, pp.279-280, Design, Automation and Test in Europe (DATE'05) Volume 1, 2005

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