Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04) At-Speed Testing of SOC ICs Paris, France February 16-February 20 ISBN: 0-7695-2085-5
This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results from Static Timing Analysis is presented. The paper also describes the usage of a clock control module on J750 tester, which creates fast clock by combining two tester channels with high edge placement accuracy. These methods allow a short test pattern preparation time and the use of low-cost test equipment, while providing the high quality at-speed testing.
Citation:
Vlado Vorisek, Thomas Koch, Hermann Fischer, "At-Speed Testing of SOC ICs," date, vol. 3, pp.30120, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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