Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04) The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) Paris, France February 16-February 20 ISBN: 0-7695-2085-5
After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.
Citation:
Luigi Dadda, Marco Macchetti, Jeff Owen, "The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)," date, vol. 3, pp.30070, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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