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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
ASCII Text
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Pallav Gupta, Niraj K. Jha, "An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 20974, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.
 
 
BibTex
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@article{ 10.1109/DATE.2004.1269019,
author = {Pallav Gupta and Niraj K. Jha},
title = {An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {2},
year = {2004},
issn = {1530-1591},
pages = {20974},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269019},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology
SN - 1530-1591
SP
EP
A1 - Pallav Gupta,
A1 - Niraj K. Jha,
PY - 2004
KW - null
VL - 2
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Pallav Gupta, Princeton University
Niraj K. Jha, Princeton University
In this paper, we describe an algorithm to post-process a register-transfer level (RTL) architecture to enable gate-level pipelining or nano-pipelining for the nanotechnology based on resonant tunneling diodes (RTDs). Nano-pipelining offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing (DSP). Since RTDs are a self-latching nanotechnology, nano-pipelining is an implicit property that should be exploited for this technology. The novelty of this work lies in exploring and demonstrating the benefits of nano-pipelining and presenting an algorithm for architectural nano-pipelining.
Citation:
Pallav Gupta, Niraj K. Jha, "An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology," date, vol. 2, pp.20974, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
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