A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk

D
DATE
2004
Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Abstract - A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk

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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	J. L. Rosselló, J. Segura, "A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 20954, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1269016, author = {J. L. Rosselló and J. Segura}, title = {A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2004}, issn = {1530-1591}, pages = {20954}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269016}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk SN - 1530-1591 SP EP A1 - J. L. Rosselló, A1 - J. Segura, PY - 2004 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

J. L. Rosselló, Balearic Islands University

J. Segura, Balearic Islands University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269016

We present a compact, fully physical, analytical model for the propagation delay and the output transition time of deep-submicron CMOS gates. The model accounts for crosstalk effects, short-circuit currents, the input-output coupling capacitance and carrier velocity saturation effects. It is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE simulations and other previously published models for different submicron technologies show significant improvements in terms of accuracy.

Citation:

J. L. Rosselló, J. Segura, "A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk," date, vol. 2, pp.20954, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004

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