Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04) An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration Paris, France February 16-February 20 ISBN: 0-7695-2085-5
In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm2 in a 0.13?m technology, and runs at 500 MHz.
Citation:
Andrei Rădulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, Paul Wielage, "An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration," date, vol. 2, pp.20878, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||