An Asynchronous Synthesis Toolset Using Verilog

D
DATE
2004
Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
Abstract - An Asynchronous Synthesis Toolset Using Verilog

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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)

An Asynchronous Synthesis Toolset Using Verilog (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Frank Burns, Delong Shang, Albert Koelmans, Alex Yakovlev, "An Asynchronous Synthesis Toolset Using Verilog," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10724, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268948, author = {Frank Burns and Delong Shang and Albert Koelmans and Alex Yakovlev}, title = {An Asynchronous Synthesis Toolset Using Verilog}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10724}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268948}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - An Asynchronous Synthesis Toolset Using Verilog SN - 1530-1591 SP EP A1 - Frank Burns, A1 - Delong Shang, A1 - Albert Koelmans, A1 - Alex Yakovlev, PY - 2004 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Frank Burns, University of Newcastle Upon Tyne

Delong Shang, University of Newcastle Upon Tyne

Albert Koelmans, University of Newcastle Upon Tyne

Alex Yakovlev, University of Newcastle Upon Tyne

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268948

We present a new CAD tool set for generating asynchronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits using David Cells (DCs). Finally logic optimization tools are applied to generate speed independent (SI) circuits. The speed independent circuits generated perform well compared to circuits generated by existing asynchronous tools.

Citation:

Frank Burns, Delong Shang, Albert Koelmans, Alex Yakovlev, "An Asynchronous Synthesis Toolset Using Verilog," date, vol. 1, pp.10724, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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