Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum) HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder Munich, Germany March 03-March 07 ISBN: 0-7695-1870-2
In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VLD algorithms. Remaining parts were realized in SW with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.
Citation:
Matjaz Verderber, Andrej Zemva, Damjan Lampret, "HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder," date, vol. 2, pp.20238, Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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