D
DATE
2003
Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Abstract - Micro-Network for SoC: Implementation of a 32-Port SPIN network

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Adrijean Andriahantenaina Articles by Alain Greiner

Design, Automation and Test in Europe Conference and Exhibition (DATE'03)

Micro-Network for SoC: Implementation of a 32-Port SPIN network (PDF)

Munich, Germany

March 03-March 07

ISBN: 0-7695-1870-2

	ASCII Text	x
	Adrijean Andriahantenaina, Alain Greiner, "Micro-Network for SoC: Implementation of a 32-Port SPIN network," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 11128, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.

	BibTex	x
	@article{ 10.1109/DATE.2003.10195, author = {Adrijean Andriahantenaina and Alain Greiner}, title = {Micro-Network for SoC: Implementation of a 32-Port SPIN network}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2003}, issn = {1530-1591}, pages = {11128}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10195}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Micro-Network for SoC: Implementation of a 32-Port SPIN network SN - 1530-1591 SP EP A1 - Adrijean Andriahantenaina, A1 - Alain Greiner, PY - 2003 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Adrijean Andriahantenaina, Pierre and Marie Curie University

Alain Greiner, Pierre and Marie Curie University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10195

We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 mm², for a cumulated bandwidth of about 100 Gbits/s. In a 6 metal process, all the routing wires can be routed on top of the switching components. The SPIN32 macro-cell will be fabricated by ST Microelectronics, but this macrocell uses symbolic layout, and can be manufactured with any CMOS process including 6 metal layers.

Citation:

Adrijean Andriahantenaina, Alain Greiner, "Micro-Network for SoC: Implementation of a 32-Port SPIN network," date, vol. 1, pp.11128, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.