Heterogeneous Programmable Logic Block Architectures

D
DATE
2003
Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Abstract - Heterogeneous Programmable Logic Block Architectures

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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)

Heterogeneous Programmable Logic Block Architectures (PDF)

Munich, Germany

March 03-March 07

ISBN: 0-7695-1870-2

	ASCII Text	x
	A. Koorapaty, V. Chandra, K. Y. Tong, C. Patel, L. Pileggi, H. Schmit, "Heterogeneous Programmable Logic Block Architectures," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 11118, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.

	BibTex	x
	@article{ 10.1109/DATE.2003.10174, author = {A. Koorapaty and V. Chandra and K. Y. Tong and C. Patel and L. Pileggi and H. Schmit}, title = {Heterogeneous Programmable Logic Block Architectures}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2003}, issn = {1530-1591}, pages = {11118}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10174}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Heterogeneous Programmable Logic Block Architectures SN - 1530-1591 SP EP A1 - A. Koorapaty, A1 - V. Chandra, A1 - K. Y. Tong, A1 - C. Patel, A1 - L. Pileggi, A1 - H. Schmit, PY - 2003 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

A. Koorapaty, Carnegie Mellon University

V. Chandra, Carnegie Mellon University

K. Y. Tong, Carnegie Mellon University

C. Patel, Carnegie Mellon University

L. Pileggi, Carnegie Mellon University

H. Schmit, Carnegie Mellon University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10174

In this poster,we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and logic gates. We demonstrate that these PLBs offer significant performance and density benefits over more homogeneous PLBs.

Citation:

A. Koorapaty, V. Chandra, K. Y. Tong, C. Patel, L. Pileggi, H. Schmit, "Heterogeneous Programmable Logic Block Architectures," date, vol. 1, pp.11118, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003

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