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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
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Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins, "Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10296, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.
 
 
BibTex
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@article{ 10.1109/DATE.2003.10035,
author = {Bingfeng Mei and Serge Vernalde and Diederik Verkest and Hugo De Man and Rudy Lauwereins},
title = {Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2003},
issn = {1530-1591},
pages = {10296},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10035},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
SN - 1530-1591
SP
EP
A1 - Bingfeng Mei,
A1 - Serge Vernalde,
A1 - Diederik Verkest,
A1 - Hugo De Man,
A1 - Rudy Lauwereins,
PY - 2003
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Bingfeng Mei, IMEC vzw and Katholic Universiteit Leuven
Serge Vernalde, IMEC vzw
Diederik Verkest, IMEC vzw and Vrije Universiteit Brussel
Hugo De Man, IMEC vzw and Katholic Universiteit Leuven
Rudy Lauwereins, IMEC vzw and Katholic Universiteit Leuven
Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures. This algorithm is a key part of our Dynamically Reconfigurable Embedded Systems Compiler (DRESC). It is capable of solving placement, scheduling and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture representation to model a wide class of coarse-grained architectures. The experimental results show high performance and efficient resource utilization on tested kernels.
Citation:
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins, "Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling," date, vol. 1, pp.10296, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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