Virtual Fault Simulation of Distributed IP-Based Designs

D
DATE
2000
Design, Automation and Test in Europe (DATE '00)
Abstract - Virtual Fault Simulation of Distributed IP-Based Designs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by M. Dalpasso Articles by A. Bogliolo Articles by L. Benini Articles by M. Favalli

Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

	ASCII Text	x
	M. Dalpasso, A. Bogliolo, L. Benini, M. Favalli, "Virtual Fault Simulation of Distributed IP-Based Designs," Design, Automation and Test in Europe Conference and Exhibition, pp. 99, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840023, author = {M. Dalpasso and A. Bogliolo and L. Benini and M. Favalli}, title = {Virtual Fault Simulation of Distributed IP-Based Designs}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {99}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840023}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Virtual Fault Simulation of Distributed IP-Based Designs SN - 1530-1591 SP EP A1 - M. Dalpasso, A1 - A. Bogliolo, A1 - L. Benini, A1 - M. Favalli, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840023

Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.

Citation:

M. Dalpasso, A. Bogliolo, L. Benini, M. Favalli, "Virtual Fault Simulation of Distributed IP-Based Designs," date, pp.99, Design, Automation and Test in Europe (DATE '00), 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.