Digital MOS Circuit Partitioning with Symbolic Modeling

D
DATE
1999
Design, Automation and Test in Europe (DATE '99)
Abstract - Digital MOS Circuit Partitioning with Symbolic Modeling

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Lluis Ribas Articles by Jordi Carrabina

Design, Automation and Test in Europe (DATE '99)

Munich, Germany

March 09-March 12

ISBN: 0-7695-0078-1

	ASCII Text	x
	Lluis Ribas, Jordi Carrabina, "Digital MOS Circuit Partitioning with Symbolic Modeling," Design, Automation and Test in Europe Conference and Exhibition, pp. 503, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761173, author = {Lluis Ribas and Jordi Carrabina}, title = {Digital MOS Circuit Partitioning with Symbolic Modeling}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {503}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761173}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Digital MOS Circuit Partitioning with Symbolic Modeling SN - 1530-1591 SP EP A1 - Lluis Ribas, A1 - Jordi Carrabina, PY - 1999 KW - circuit partitioning KW - switch-level circuit analysis KW - symbolic circuit traversal KW - symbolic modeling VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Lluis Ribas, Autonomous University of Barcelona (UAB)

Jordi Carrabina, Autonomous University of Barcelona (UAB)

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761173

This paper presents a method to automatically recognize and model single and multi-output logic gates out of a switch-level network, even for irregular transistor structures. Result subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.

Index Terms:

circuit partitioning, switch-level circuit analysis, symbolic circuit traversal, symbolic modeling

Citation:

Lluis Ribas, Jordi Carrabina, "Digital MOS Circuit Partitioning with Symbolic Modeling," date, pp.503, Design, Automation and Test in Europe (DATE '99), 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.