A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine

D
DATE
1999
Design, Automation and Test in Europe (DATE '99)
Abstract - A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine

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Design, Automation and Test in Europe (DATE '99)

Munich, Germany

March 09-March 12

ISBN: 0-7695-0078-1

	ASCII Text	x
	Hisashi Sasaki, "A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine," Design, Automation and Test in Europe Conference and Exhibition, pp. 353, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761145, author = {Hisashi Sasaki}, title = {A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {353}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761145}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine SN - 1530-1591 SP EP A1 - Hisashi Sasaki, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Hisashi Sasaki

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761145

Citation:

Hisashi Sasaki, "A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine," date, pp.353, Design, Automation and Test in Europe (DATE '99), 1999

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