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Design Automation and Test in Europe (DATE '98)
Formal Specification in VHDL for Hardware Verification
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
ASCII Text
x 
 
Ralf Reetz, Klaus Schneider, Thomas Kropf, "Formal Specification in VHDL for Hardware Verification," Design, Automation and Test in Europe Conference and Exhibition, pp. 257, Design Automation and Test in Europe (DATE '98), 1998.
 
 
BibTex
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@article{ 10.1109/DATE.1998.655865,
author = {Ralf Reetz and Klaus Schneider and Thomas Kropf},
title = {Formal Specification in VHDL for Hardware Verification},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1998},
isbn = {0-8186-8359-7},
pages = {257},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655865},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Formal Specification in VHDL for Hardware Verification
SN - 0-8186-8359-7
SP
EP
A1 - Ralf Reetz,
A1 - Klaus Schneider,
A1 - Thomas Kropf,
PY - 1998
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Ralf Reetz, Verysys GmbH
Klaus Schneider, Universit? at Karlsruhe
Thomas Kropf, Universit? at Karlsruhe
In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As the specifications are independent from a certain formalism, there is no restriction to a certain hardware verification approach.
Citation:
Ralf Reetz, Klaus Schneider, Thomas Kropf, "Formal Specification in VHDL for Hardware Verification," date, pp.257, Design Automation and Test in Europe (DATE '98), 1998
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