Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation

A
ACSD
2001
Second International Conference on Application of Concurrency to System Design (ACSD'01)
Abstract - Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by O. Garnica Articles by J. Lanchares Articles by R. Hermida

Second International Conference on Application of Concurrency to System Design (ACSD'01)

Newcastle upon Tyne, UK

June 25-June 29

ISBN: 0-7695-1071-X

	ASCII Text	x
	O. Garnica, J. Lanchares, R. Hermida, "Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation," Application of Concurrency to System Design, International Conference on, pp. 167, Second International Conference on Application of Concurrency to System Design (ACSD'01), 2001.

	BibTex	x
	@article{ 10.1109/CSD.2001.981774, author = {O. Garnica and J. Lanchares and R. Hermida}, title = {Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation}, journal ={Application of Concurrency to System Design, International Conference on}, volume = {0}, year = {2001}, isbn = {0-7695-1071-X}, pages = {167}, doi = {http://doi.ieeecomputersociety.org/10.1109/CSD.2001.981774}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application of Concurrency to System Design, International Conference on TI - Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation SN - 0-7695-1071-X SP EP A1 - O. Garnica, A1 - J. Lanchares, A1 - R. Hermida, PY - 2001 VL - 0 JA - Application of Concurrency to System Design, International Conference on ER -

O. Garnica, Universidad Complutense de Madrid

J. Lanchares, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSD.2001.981774

This paper is devoted to studying two key issues of the asynchronous pipelines: their performance, and the influence that the position of stages have on the latency of a pipelined asynchronous circuit as a whole. To attain the performance evaluation, we derive expressions of the latency and the cycle time of a linear pipeline as closed-form formulas. To attain the influence of the position, we present some experiments, using the previous closed-form formulas, on different pipelines.

Citation:

O. Garnica, J. Lanchares, R. Hermida, "Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation," acsd, pp.167, Second International Conference on Application of Concurrency to System Design (ACSD'01), 2001

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.