The Scalability Port (SP) is a point-to-point cache consistent interface to build scalable shared memory multiprocessors. The SP interface consists of three layers of abstraction: the Physical Layer, the Link Layer and the Protocol Layer. The Physical Layer uses pin-efficient simultaneous bi-directional signaling and operates at 800 MHz in each direction. The Link Layer supports virtual channels and provides flow control and reliable transmission. The Protocol Layer implements cache consistency, TLB consistency, synchronization, and interrupt delivery functions among others. The first implementation of the SP interface is in the Intel? E8870 and E9870 chipset for the Intel Itanium? 2 processor and future generations of the Itanium processor family [1].