A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support

H
HOTI
2002
10th Symposium on High Performance Interconnects HOT Interconnects (HotI'02)
Abstract - A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support

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	Similar Articles Articles by F. Abel Articles by C. Minkenberg Articles by R. P. Luijten Articles by M. Gusat Articles by I. Iliadis

10th Symposium on High Performance Interconnects HOT Interconnects (HotI'02)

Stanford, California, USA

August 21-August 23

ISBN: 0-7695-1650-5

	ASCII Text	x
	F. Abel, C. Minkenberg, R. P. Luijten, M. Gusat, I. Iliadis, "A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support," High-Performance Interconnects, Symposium on, pp. 5, 10th Symposium on High Performance Interconnects HOT Interconnects (HotI'02), 2002.

	BibTex	x
	@article{ 10.1109/CONECT.2002.1039251, author = {F. Abel and C. Minkenberg and R. P. Luijten and M. Gusat and I. Iliadis}, title = {A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support}, journal ={High-Performance Interconnects, Symposium on}, volume = {0}, year = {2002}, isbn = {0-7695-1650-5}, pages = {5}, doi = {http://doi.ieeecomputersociety.org/10.1109/CONECT.2002.1039251}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - High-Performance Interconnects, Symposium on TI - A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support SN - 0-7695-1650-5 SP EP A1 - F. Abel, A1 - C. Minkenberg, A1 - R. P. Luijten, A1 - M. Gusat, A1 - I. Iliadis, PY - 2002 KW - null VL - 0 JA - High-Performance Interconnects, Symposium on ER -

F. Abel, IBM Research, Zurich Research Laboratory

C. Minkenberg, IBM Research, Zurich Research Laboratory

R. P. Luijten, IBM Research, Zurich Research Laboratory

M. Gusat, IBM Research, Zurich Research Laboratory

I. Iliadis, IBM Research, Zurich Research Laboratory

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CONECT.2002.1039251

We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output queuing at the ingress, which has the scalability of input-buffered switches and the performance of output-buffered switches. Our system handles the large fabric-internal transmission latency that results from packaging up to 256 line cards into multiple racks. We provide the justification for selecting this architecture and compare it with other current solutions. With an ASIC implementation, we show that a single-stage multi-terabit buffered crossbar approach is viable today.

Citation:

F. Abel, C. Minkenberg, R. P. Luijten, M. Gusat, I. Iliadis, "A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support," hoti, pp.5, 10th Symposium on High Performance Interconnects HOT Interconnects (HotI'02), 2002

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