2008 Communication Networks and Services Research Conference (CNSR 2008) A 42-Gb/s Decision Circuit in 0.13?m CMOS May 05-May 08 ISBN: 978-0-7695-3135-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CNSR.2008.15
In this paper, a decision circuit based on 0.13 ?mCMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the robustness against common-mode disturbances. A 3-stage output buffer is employed to drive the external 50 Ω loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The decision circuit uses a single 1.2V supply and consumes a total current of 33 mA. And the chip area is only 0.63 mm^2 with bonding pads.
Index Terms:
CMOS CML, Shunt peaking, Split-resistor, Optical communication
Citation:
Bangli Liang, Tad Kwasniewski, Dianyong Chen, "A 42-Gb/s Decision Circuit in 0.13?m CMOS," cnsr, pp.339-342, 2008 Communication Networks and Services Research Conference (CNSR 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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