loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fifth IEEE International Conference on Cluster Computing (CLUSTER'03)
Implications of a PIM Architectural Model for MPI
Hong Kong
December 01-December 04
ISBN: 0-7695-2066-9
Arun Rodrigues, University of Notre Dame
Richard Murphy, University of Notre Dame
Peter Kogge, University of Notre Dame
Jay Brockman, University of Notre Dame
Ron Brightwell, Sandia National Labs
Keith Underwood, Sandia National Labs
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory (PIM) research efforts are considering ways to move processing into memory without significantly increasing the cost of the memory. As such, PIM devices may become the basis for future commodity clusters. Although these PIM devices may leverage new computational paradigms such as hardware support for multi-threading and traveling threads, they must provide support for legacy programming models if they are to supplant commodity clusters. This paper presents a prototype implementation of MPI over a traveling thread mechanism called parcels. A performance analysis indicates that the direct hardware support of a traveling thread model can lead to an efficient, lightweight MPI implementation.
Citation:
Arun Rodrigues, Richard Murphy, Peter Kogge, Jay Brockman, Ron Brightwell, Keith Underwood, "Implications of a PIM Architectural Model for MPI," cluster, pp.259, Fifth IEEE International Conference on Cluster Computing (CLUSTER'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.