Sixth IEEE International Conference on Computer and Information Technology (CIT'06)
Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems
Seoul, Korea
September 20-September 22
ISBN: 0-7695-2687-X
Wei Chen, National University of Defense Technology, China
Rui Gong, National University of Defense Technology, China
Kui Dai, National University of Defense Technology, China
Fang Liu, National University of Defense Technology, China
Zhiying Wang, National University of Defense Technology, China
Triple Modular Redundancy (TMR) is widely used to improve fault tolerance of computer systems against transient faults. Conventional TMR is effective in protecting sequential circuits but can?t mask transient faults in combinational circuits. New redundancy techniques called Space-Time TMR (ST-TMR) and Enhanced ST-TMR (EST-TMR) with double edge triggered registers are presented in this paper, which improve fault tolerance of both combinational circuits and sequential circuits. ST-TMR is effective in protecting throughput circuit while EST-TMR is effective in protecting state-machine circuit. This paper demonstrates the usefulness of ST-TMR and EST-TMR in two special case studies. The overhead and fault tolerance of ST-TMR and EST-TMR are compared with that of the conventional TMR. Results show that ST-TMR and EST-TMR are more effective.
Citation:
Wei Chen, Rui Gong, Kui Dai, Fang Liu, Zhiying Wang, "Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems," cit, pp.175, Sixth IEEE International Conference on Computer and Information Technology (CIT'06), 2006
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