International Symposium on Code Generation and Optimization (CGO'07)
Parallel Programming Environment: A Key to Translating Tera-Scale Platforms into a Big Success (PDF)
San Jose, California March 11-March 14 ISBN: 0-7695-2764-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CGO.2007.28
Moore?s Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since the power and thermal constraints increase with frequency, multi-core or many-core will be the way of the future microprocessor.
Citation:
Jesse Fang, "Parallel Programming Environment: A Key to Translating Tera-Scale Platforms into a Big Success," cgo, pp.18, International Symposium on Code Generation and Optimization (CGO'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||