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International Conference on Computer Graphics, Imaging and Visualisation (CGIV'06)
Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder
Sydney, Australia
July 26-July 28
ISBN: 0-7695-2606-3
ASCII Text
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Yuhuang Ye, Yuanjiu Li, Kaixiong Su, "Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder," Computer Graphics, Imaging and Visualization, International Conference on, pp. 226-230, International Conference on Computer Graphics, Imaging and Visualisation (CGIV'06), 2006.
 
 
BibTex
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@article{ 10.1109/CGIV.2006.23,
author = {Yuhuang Ye and Yuanjiu Li and Kaixiong Su},
title = {Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder},
journal ={Computer Graphics, Imaging and Visualization, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2606-3},
pages = {226-230},
doi = {http://doi.ieeecomputersociety.org/10.1109/CGIV.2006.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Graphics, Imaging and Visualization, International Conference on
TI - Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder
SN - 0-7695-2606-3
SP226
EP230
A1 - Yuhuang Ye,
A1 - Yuanjiu Li,
A1 - Kaixiong Su,
PY - 2006
KW - HDTV
KW - MPEG-2
KW - video decoder
KW - set top box
VL - 0
JA - Computer Graphics, Imaging and Visualization, International Conference on
ER -
 
Yuhuang Ye, Fuzhou University, China
Yuanjiu Li, Fuzhou University, China
Kaixiong Su, Fuzhou University, China
This paper presents the architecture and software design of HDTV video decoder on a 200-MHz single-chip microprocessor. First, the paper analyzes the hardware architecture of video decoder system on this MPEG decoder and describes the function of each module in this system, including the PES Parser, Decode pipeline, SC Analyzer, and Display Processor. Then it gives the software control and implementation of this video decoder. This video decoder meets the requirements for MPEG-2 MP@HL real-time decoding. The outcome of this paper should be helpful to the design of HDTV Set Top Box.
Index Terms:
HDTV, MPEG-2, video decoder, set top box
Citation:
Yuhuang Ye, Yuanjiu Li, Kaixiong Su, "Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder," cgiv, pp.226-230, International Conference on Computer Graphics, Imaging and Visualisation (CGIV'06), 2006
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