21st International Conference on Distributed Computing Systems Workshops (ICDCSW '01) LART: Flexible, Low-Power Building Blocks for Wearable Computers Mesa, Arizona April 16-April 19 ISBN: 0-7695-1080-9
Abstract: To ease the implementation of different wearable computers, we developed a low-power processor board (named LART) with a rich set of interfaces. The LART supports dynamic voltage scaling, so performance (and power consumption) can be scaled to match demands: 59-221 MHz, 106-640 mW. High-end wearables can be configured from multiple LARTs operating in parallel; alternatively, FPGA boards can be used for dedicated data-processing, which reduces power consumption significantly.
Citation:
Jan-Derk Bakker, Koen Langendoen, Henk Sips, "LART: Flexible, Low-Power Building Blocks for Wearable Computers," icdcsw, pp.0255, 21st International Conference on Distributed Computing Systems Workshops (ICDCSW '01), 2001 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||