This paper describes how asynchronous techniques make easier timing in an image processing computer. It outlines an original machine architecture, and explains why it is asynchronous: the router circuit supports the asynchronism by itself. Its structure and behavior are sketched. Our method for self-timed design, its salient features and contributions to the typical asynchronous circuit design flow are introduced. The VLSI implementation and the cell set design, including full-custom self-timed asynchronous cells, are detailed. Measured circuit's performances are presented, as well as global processing and communication performances for different image processing algorithms. The gain from asynchronism is exhibited.