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Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures
Padova, Italy
September 11-September 13
ISBN: 0-7695-0740-9
ASCII Text
x 
 
N. Zingirian, M. Maresca, "Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures," Computer Architectures for Machine Perception, International Workshop on, pp. 261, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000.
 
 
BibTex
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@article{ 10.1109/CAMP.2000.875985,
author = {N. Zingirian and M. Maresca},
title = {Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures},
journal ={Computer Architectures for Machine Perception, International Workshop on},
volume = {0},
year = {2000},
isbn = {0-7695-0740-9},
pages = {261},
doi = {http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875985},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Architectures for Machine Perception, International Workshop on
TI - Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures
SN - 0-7695-0740-9
SP
EP
A1 - N. Zingirian,
A1 - M. Maresca,
PY - 2000
KW - embedded systems; loop regularization; video processing; image processing; instruction level parallel architectures; instruction reordering; register renaming; embedded systems; digital signal processors
VL - 0
JA - Computer Architectures for Machine Perception, International Workshop on
ER -
 
N. Zingirian, Dipt. di Elettronica e Inf., Padova Univ., Italy
M. Maresca, Dipt. di Elettronica e Inf., Padova Univ., Italy
This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today's low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.
Index Terms:
embedded systems; loop regularization; video processing; image processing; instruction level parallel architectures; instruction reordering; register renaming; embedded systems; digital signal processors
Citation:
N. Zingirian, M. Maresca, "Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures," camp, pp.261, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000
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