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Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?
Padova, Italy
September 11-September 13
ISBN: 0-7695-0740-9
ASCII Text
x 
 
D. Demigny, L. Kessal, R. Bourguiba, N. Boudouani, "How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?," Computer Architectures for Machine Perception, International Workshop on, pp. 240, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000.
 
 
BibTex
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@article{ 10.1109/CAMP.2000.875983,
author = {D. Demigny and L. Kessal and R. Bourguiba and N. Boudouani},
title = {How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?},
journal ={Computer Architectures for Machine Perception, International Workshop on},
volume = {0},
year = {2000},
isbn = {0-7695-0740-9},
pages = {240},
doi = {http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875983},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Architectures for Machine Perception, International Workshop on
TI - How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?
SN - 0-7695-0740-9
SP
EP
A1 - D. Demigny,
A1 - L. Kessal,
A1 - R. Bourguiba,
A1 - N. Boudouani,
PY - 2000
KW - image segmentation; high speed reconfigurable FPGA; real time image processing; hardware architecture; ARDOISE; video frame duration; architectural concepts; image segmentation; partitioning methodology
VL - 0
JA - Computer Architectures for Machine Perception, International Workshop on
ER -
 
D. Demigny, Cergy Pontoise Univ., France
L. Kessal, Cergy Pontoise Univ., France
R. Bourguiba, Cergy Pontoise Univ., France
N. Boudouani, Cergy Pontoise Univ., France
In France, ten research teams study and build a hardware architecture (ARDOISE) which is dedicated to real time image processing. This architecture uses fast or dynamic reconfiguration allowed by new FPGA circuits. During a video frame duration, several algorithms are computed sequentially on the same hardware. This paper highlights the architectural concepts used to build ARDOISE. Then an analytical model is defined in order to complete the limits and the performances expected in the use of the dynamic reconfiguration scheme. An example in image segmentation is developed to show a possible partitioning methodology.
Index Terms:
image segmentation; high speed reconfigurable FPGA; real time image processing; hardware architecture; ARDOISE; video frame duration; architectural concepts; image segmentation; partitioning methodology
Citation:
D. Demigny, L. Kessal, R. Bourguiba, N. Boudouani, "How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?," camp, pp.240, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000
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