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Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Compiling and Optimizing Image Processing Algorithms for FPGAs
Padova, Italy
September 11-September 13
ISBN: 0-7695-0740-9
ASCII Text
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B. Draper, W. Najjar, W. Bohm, J. Hammes, B. Rinker, C. Ross, M. Chawathe, J. Bins, "Compiling and Optimizing Image Processing Algorithms for FPGAs," Computer Architectures for Machine Perception, International Workshop on, pp. 222, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000.
 
 
BibTex
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@article{ 10.1109/CAMP.2000.875981,
author = {B. Draper and W. Najjar and W. Bohm and J. Hammes and B. Rinker and C. Ross and M. Chawathe and J. Bins},
title = {Compiling and Optimizing Image Processing Algorithms for FPGAs},
journal ={Computer Architectures for Machine Perception, International Workshop on},
volume = {0},
year = {2000},
isbn = {0-7695-0740-9},
pages = {222},
doi = {http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875981},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Architectures for Machine Perception, International Workshop on
TI - Compiling and Optimizing Image Processing Algorithms for FPGAs
SN - 0-7695-0740-9
SP
EP
A1 - B. Draper,
A1 - W. Najjar,
A1 - W. Bohm,
A1 - J. Hammes,
A1 - B. Rinker,
A1 - C. Ross,
A1 - M. Chawathe,
A1 - J. Bins,
PY - 2000
KW - data flow graphs; image processing algorithms; FPGAs; high-level language; optimizing compiler; SA-C; language features; SA-C algorithms; data flow graphs; VHDL; performance numbers; image processing routines; Annapolis Microsystems WildForce board; Xilinx 4036XL FPGAs
VL - 0
JA - Computer Architectures for Machine Perception, International Workshop on
ER -
 
B. Draper, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
W. Najjar, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
W. Bohm, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
J. Hammes, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
B. Rinker, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
C. Ross, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
M. Chawathe, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
J. Bins, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.
Index Terms:
data flow graphs; image processing algorithms; FPGAs; high-level language; optimizing compiler; SA-C; language features; SA-C algorithms; data flow graphs; VHDL; performance numbers; image processing routines; Annapolis Microsystems WildForce board; Xilinx 4036XL FPGAs
Citation:
B. Draper, W. Najjar, W. Bohm, J. Hammes, B. Rinker, C. Ross, M. Chawathe, J. Bins, "Compiling and Optimizing Image Processing Algorithms for FPGAs," camp, pp.222, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000
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