A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology

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	Similar Articles Articles by M. Aberbour Articles by H. Mehrez Articles by F. Durbin Articles by J. Haussy Articles by P. Lalande Articles by A. Tissot

Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)

Padova, Italy

September 11-September 13

ISBN: 0-7695-0740-9

	ASCII Text	x
	M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot, "A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology," Computer Architectures for Machine Perception, International Workshop on, pp. 155, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000.

	BibTex	x
	@article{ 10.1109/CAMP.2000.875973, author = {M. Aberbour and H. Mehrez and F. Durbin and J. Haussy and P. Lalande and A. Tissot}, title = {A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology}, journal ={Computer Architectures for Machine Perception, International Workshop on}, volume = {0}, year = {2000}, isbn = {0-7695-0740-9}, pages = {155}, doi = {http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875973}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Architectures for Machine Perception, International Workshop on TI - A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology SN - 0-7695-0740-9 SP EP A1 - M. Aberbour, A1 - H. Mehrez, A1 - F. Durbin, A1 - J. Haussy, A1 - P. Lalande, A1 - A. Tissot, PY - 2000 KW - pattern recognition; system-on-a-chip; pattern recognition architecture; design methodology; specification; heterogeneous architecture; hardware/software codesign; system architecture; VLSI physical integration; VLSI characteristics VL - 0 JA - Computer Architectures for Machine Perception, International Workshop on ER -

M. Aberbour, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

H. Mehrez, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

F. Durbin, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

J. Haussy, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

P. Lalande, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

A. Tissot, Lab. LIP6/ASIM, Univ. Pierre et Marie Curie, Paris, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875973

We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.

Index Terms:

pattern recognition; system-on-a-chip; pattern recognition architecture; design methodology; specification; heterogeneous architecture; hardware/software codesign; system architecture; VLSI physical integration; VLSI characteristics

Citation:

M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot, "A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology," camp, pp.155, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000

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