An FPGA Architecture for High Speed Edge and Corner Detection

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	Similar Articles Articles by C. Torres-Huitzil Articles by M. Arias-Estrada

Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)

Padova, Italy

September 11-September 13

ISBN: 0-7695-0740-9

	ASCII Text	x
	C. Torres-Huitzil, M. Arias-Estrada, "An FPGA Architecture for High Speed Edge and Corner Detection," Computer Architectures for Machine Perception, International Workshop on, pp. 112, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000.

	BibTex	x
	@article{ 10.1109/CAMP.2000.875965, author = {C. Torres-Huitzil and M. Arias-Estrada}, title = {An FPGA Architecture for High Speed Edge and Corner Detection}, journal ={Computer Architectures for Machine Perception, International Workshop on}, volume = {0}, year = {2000}, isbn = {0-7695-0740-9}, pages = {112}, doi = {http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875965}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Architectures for Machine Perception, International Workshop on TI - An FPGA Architecture for High Speed Edge and Corner Detection SN - 0-7695-0740-9 SP EP A1 - C. Torres-Huitzil, A1 - M. Arias-Estrada, PY - 2000 KW - computer vision; FPGA architecture; corner detection; edge detection; high speed; computer vision; architecture design; FPGA resources utilization VL - 0 JA - Computer Architectures for Machine Perception, International Workshop on ER -

C. Torres-Huitzil, Nat. Inst. for Astrophys., Opt. & Electron., Puebla, Mexico

M. Arias-Estrada, Nat. Inst. for Astrophys., Opt. & Electron., Puebla, Mexico

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CAMP.2000.875965

This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.

Index Terms:

computer vision; FPGA architecture; corner detection; edge detection; high speed; computer vision; architecture design; FPGA resources utilization

Citation:

C. Torres-Huitzil, M. Arias-Estrada, "An FPGA Architecture for High Speed Edge and Corner Detection," camp, pp.112, Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00), 2000

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