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16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'04)
Multi-Profile Instruction Based Compression
Foz do Igua?u, PR - Brazil
October 27-October 29
ISBN: 0-7695-2240-8
ASCII Text
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Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo, "Multi-Profile Instruction Based Compression," Computer Architecture and High Performance Computing, Symposium on, pp. 23-29, 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'04), 2004.
 
 
BibTex
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@article{ 10.1109/CAHPC.2004.26,
author = {Eduardo Wanderley Netto and Rodolfo Azevedo and Paulo Centoducatte and Guido Araujo},
title = {Multi-Profile Instruction Based Compression},
journal ={Computer Architecture and High Performance Computing, Symposium on},
volume = {0},
year = {2004},
issn = {1550-6533},
pages = {23-29},
doi = {http://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.26},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Architecture and High Performance Computing, Symposium on
TI - Multi-Profile Instruction Based Compression
SN - 1550-6533
SP23
EP29
A1 - Eduardo Wanderley Netto,
A1 - Rodolfo Azevedo,
A1 - Paulo Centoducatte,
A1 - Guido Araujo,
PY - 2004
KW - null
VL - 0
JA - Computer Architecture and High Performance Computing, Symposium on
ER -
 
Eduardo Wanderley Netto, CEFETRN / IC-UNICAMP, Brazil
Rodolfo Azevedo, IC-UNICAMP, Brazil
Paulo Centoducatte, IC-UNICAMP, Brazil
Guido Araujo, IC-UNICAMP, Brazil
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-product of compression. In this paper we propose a novel technique for efficiently exploring the trade-offs involved in code compression. Our Multi-Profile approach to build dictionaries combines the best features of both static and dynamic program behaviors. The experiments with Mediabench and MiBench suites and the Leon (SPARCv8) processor reveals a compression ratio as low as 71% while performance speed-up reaches 1.5.
Citation:
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo, "Multi-Profile Instruction Based Compression," sbac-pad, pp.23-29, 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'04), 2004
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