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14th Asian Test Symposium (ATS'05)
Random Jitter Testing Using Low Tap-Count Delay Lines
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
ASCII Text
x 
 
Jiun-Lang Huang, "Random Jitter Testing Using Low Tap-Count Delay Lines," Asian Test Symposium, pp. 100-105, 14th Asian Test Symposium (ATS'05), 2005.
 
 
BibTex
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@article{ 10.1109/ATS.2005.93,
author = {Jiun-Lang Huang},
title = {Random Jitter Testing Using Low Tap-Count Delay Lines},
journal ={Asian Test Symposium},
volume = {0},
year = {2005},
issn = {1081-7735},
pages = {100-105},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2005.93},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Random Jitter Testing Using Low Tap-Count Delay Lines
SN - 1081-7735
SP100
EP105
A1 - Jiun-Lang Huang,
PY - 2005
KW - High-speed serial transmission
KW - design-fortest
KW - jitter testing.
VL - 0
JA - Asian Test Symposium
ER -
 
Jiun-Lang Huang, National Taiwan University, Taipei, Taiwan
In this paper, a low-cost and process-insensitive random jitter testing algorithm is proposed for on-chip design-fortest applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations.
Index Terms:
High-speed serial transmission, design-fortest,jitter testing.
Citation:
Jiun-Lang Huang, "Random Jitter Testing Using Low Tap-Count Delay Lines," ats, pp.100-105, 14th Asian Test Symposium (ATS'05), 2005
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