Due to advances in processing technology, modern Systems-on-chip (SoC) devices can incorporate highspeed digital, memory, analog, and RF circuits on a single chip. This high integration of components makes SoC testing complex and costly. Conventional ATE testing for mixed-signal and RF devices requires the use of dedicated and expensive analog resources.

Analog and RF testing poses major challenges that have yet to be surmounted. There are several reasons for the inherent complexity of analog and RF testing: a lack of analog fault models hinders structural testing approaches, and there is no coverage metric in place for analog and RF testing.

Currently within the industry, analog and RF functional testing to specification is carried out to ensure that DPM goals are being met. This testing approach is increasingly expensive and is fast becoming impractical. Analog and RF DFT is an alternative approach for testing these products.