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14th Asian Test Symposium (ATS'05)
A Family of Logical Fault Models for Reversible Circuits
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
Ilia Polian, Albert-Ludwigs-University, Germany
Thomas Fiehn, Albert-Ludwigs-University, Germany
Bernd Becker, Albert-Ludwigs-University, Germany
John P. Hayes, University of Michigan, USA
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
Index Terms:
ATPG, fault models, reversible circuits,quantum circuits
Citation:
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes, "A Family of Logical Fault Models for Reversible Circuits," ats, pp.422-427, 14th Asian Test Symposium (ATS'05), 2005
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