This paper presents a design-for-testability method that transforms a given SoC into consecutively testable one under power constraint. When a power constraint and a user defined importance ratio between area overhead and test time are given, the proposed method can create an optimal TAM design and a test schedule for the importance ratio under the power constraint with low computational cost. Experimental results show that the proposed method can achieve area and time co-optimization under power constraint. Moreover, the proposed method can obtain better results for SoCs without power constraint compared to test bus method and our previous method based on consecutive testability of SoCs.