loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
14th Asian Test Symposium (ATS'05)
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
ASCII Text
x 
 
V R Devanathan, "Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage," Asian Test Symposium, pp. 300-305, 14th Asian Test Symposium (ATS'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/ATS.2005.82,
author = {V R Devanathan},
title = {Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage},
journal ={Asian Test Symposium},
volume = {0},
year = {2005},
issn = {1081-7735},
pages = {300-305},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2005.82},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage
SN - 1081-7735
SP300
EP305
A1 - V R Devanathan,
PY - 2005
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
V R Devanathan, Texas Instruments, Bangalore
In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.
Citation:
V R Devanathan, "Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage," ats, pp.300-305, 14th Asian Test Symposium (ATS'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.