Traditional approaches to memory test and repair depended on external memory testers and general-purpose redundancy allocation software to repair the memories. However, the size and complexity of today?s SoCs and the soaring cost of test has made these approaches almost obsolete, because they are specific to each device and provide only a limited value in silicon bring-up and diagnosis. To address this challenge semiconductor IP vendors have introduced special embedded IP called infrastructure IPs (IIP). . Examples of such infrastructure IP include built-in Self-test (BIST) for logic and memories, built-in repair-analysis (BIRA), built-in self-repair (BISR), and error correcting codes (ECC) for embedded memories, etc. This presentation will discuss one such IIP targeted towards the test and repair of embedded memories.