This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within randomtest pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns and bits. LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures. The experimental results for ISCAS?85 and ?89 benchmarks, con- firm up to 77% and 49% reduction in average and peak power, respectively.