Low Power Test Compression Technique for Designs with Multiple Scan Chain

A
ATS
2005
14th Asian Test Symposium (ATS'05)
Abstract - Low Power Test Compression Technique for Designs with Multiple Scan Chain

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	Similar Articles Articles by Youhua Shi Articles by Nozomu Togawa Articles by Masao Yanagisawa Articles by Tatsuo Ohtsuki Articles by Shinji Kimura

14th Asian Test Symposium (ATS'05)

Calcutta, India

December 18-December 21

ISBN: 0-7695-2481-8

	ASCII Text	x
	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura, "Low Power Test Compression Technique for Designs with Multiple Scan Chain," Asian Test Symposium, pp. 386-389, 14th Asian Test Symposium (ATS'05), 2005.

	BibTex	x
	@article{ 10.1109/ATS.2005.76, author = {Youhua Shi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki and Shinji Kimura}, title = {Low Power Test Compression Technique for Designs with Multiple Scan Chain}, journal ={Asian Test Symposium}, volume = {0}, year = {2005}, issn = {1081-7735}, pages = {386-389}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2005.76}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Low Power Test Compression Technique for Designs with Multiple Scan Chain SN - 1081-7735 SP386 EP389 A1 - Youhua Shi, A1 - Nozomu Togawa, A1 - Masao Yanagisawa, A1 - Tatsuo Ohtsuki, A1 - Shinji Kimura, PY - 2005 KW - null VL - 0 JA - Asian Test Symposium ER -

Youhua Shi, Waseda University, Japan

Nozomu Togawa, Waseda University, Japan

Masao Yanagisawa, Waseda University, Japan

Tatsuo Ohtsuki, Waseda University, Japan

Shinji Kimura, Grad. School of Infomation, Production and Systems, Waseda University, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2005.76

This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with a pre-computed test cube set and fill the don?t-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS?89 benchmarks show the efficiency of the proposed technique.

Citation:

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura, "Low Power Test Compression Technique for Designs with Multiple Scan Chain," ats, pp.386-389, 14th Asian Test Symposium (ATS'05), 2005

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