Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

A
ATS
2005
14th Asian Test Symposium (ATS'05)
Abstract - Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Hiroyuki Nakamura Articles by Akio Shirokane Articles by Yoshihito Nishizaki Articles by Anis Uzzaman Articles by Vivek Chickermane Articles by Brion Keller Articles by Tsutomu Ube Articles by Yoshihiko Terauchi

14th Asian Test Symposium (ATS'05)

Calcutta, India

December 18-December 21

ISBN: 0-7695-2481-8

	ASCII Text	x
	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion Keller, Tsutomu Ube, Yoshihiko Terauchi, "Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression," Asian Test Symposium, pp. 156-161, 14th Asian Test Symposium (ATS'05), 2005.

	BibTex	x
	@article{ 10.1109/ATS.2005.75, author = {Hiroyuki Nakamura and Akio Shirokane and Yoshihito Nishizaki and Anis Uzzaman and Vivek Chickermane and Brion Keller and Tsutomu Ube and Yoshihiko Terauchi}, title = {Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression}, journal ={Asian Test Symposium}, volume = {0}, year = {2005}, issn = {1081-7735}, pages = {156-161}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2005.75}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression SN - 1081-7735 SP156 EP161 A1 - Hiroyuki Nakamura, A1 - Akio Shirokane, A1 - Yoshihito Nishizaki, A1 - Anis Uzzaman, A1 - Vivek Chickermane, A1 - Brion Keller, A1 - Tsutomu Ube, A1 - Yoshihiko Terauchi, PY - 2005 KW - null VL - 0 JA - Asian Test Symposium ER -

Hiroyuki Nakamura, Kawasaki Microelectronics

Akio Shirokane, Kawasaki Microelectronics

Yoshihito Nishizaki, Kawasaki Microelectronics

Anis Uzzaman, Cadence Design Systems, Inc

Vivek Chickermane, Cadence Design Systems, Inc

Brion Keller, Cadence Design Systems, Inc

Tsutomu Ube, Innotech Corporation

Yoshihiko Terauchi, Innotech Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2005.75

Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the problem of increased test data volume due to delay tests. Data is presented on several industrial circuits to demonstrate the effectiveness of these DFT methods on nanometer designs. Our results show that a seamless combination of atspeed delay testing with compression can help to test the nanometer defects at a very competitive cost.

Citation:

Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion Keller, Tsutomu Ube, Yoshihiko Terauchi, "Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression," ats, pp.156-161, 14th Asian Test Symposium (ATS'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.