In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell and senseamplifiers. Our analysis shows that, improving robustness of senseamplifier is extremely important for reducing memory access failure probability and improving yield. We present a process variation tolerant sense amplifier suitable for SRAM array designed in sub- 100nm CMOS technologies. The proposed technique reduces the failure probability of sense amplifiers by more than 80% with negligible penalty in the sensing delay.