14th Asian Test Symposium (ATS'05) Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach Calcutta, India December 18-December 21 ISBN: 0-7695-2481-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2005.71
Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modifies the faulty behavior of the memory. This paper introduces an analytical (equation-based) method to give a rough analysis of the faulty behavior of cell opens in the memory, that simplifies the understanding and identifies the major factors responsible for the faulty behavior. Having these factors makes it easier to optimize the circuit and allows extrapolation of the behavior of future technologies. The paper also compares the results of the analytical approach with those from the simulationbased analysis and discusses the advantages and disadvantages of both.
Index Terms:
DRAMs, faulty behavior, defect simulation,analytical evaluation, memory testing.
Citation:
Zaid Al-Ars, Said Hamdioui, Jorg Vollrath, "Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach," ats, pp.434-439, 14th Asian Test Symposium (ATS'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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