As smaller technology nodes (< 90nm) are being adopted for manufacturing at a rapid pace along with an insatiable market for high quality devices, the need for test data compression cannot be overstated. With smaller line geometries, new defects are being continuously unraveled, which in turn is putting pressure on DFT engineers to consider new fault models that could detect such defects. Conventionally, the stuck-at fault model was primarily used, but as circuit sizes grew, the number of vectors to target stuck-at faults was itself stressing the limited capacity of an Automatic Test Equipment (ATE). Consequently, test cost directly related to test data volume and test application time was rising. The situation worsens when one tries to include vectors for fault models such as transition, path-delay, n-detect, bridging, etc. Each of these fault models requires patterns that are much larger than a stuck-at pattern test set. The only way to address the situation is to either swallow the higher test cost or sacrifice quality by truncating test sets to fit into the ATE vector memory.