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14th Asian Test Symposium (ATS'05)
Finite State Machine Synthesis for At-Speed Oscillation Testability
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
Katherine Shu-Min Li, National Chiao Tung University, Hsichu, Taiwan
Chung Len Lee, National Chiao Tung University, Hsichu, Taiwan
Tagin Jiang, National Chiao Tung University, Hsichu, Taiwan
Chauchin Su, National Chiao Tung University, Hsichu, Taiwan
Jwu E. Chen, National Central University, Chungli, Taiwan
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.
Citation:
Katherine Shu-Min Li, Chung Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen, "Finite State Machine Synthesis for At-Speed Oscillation Testability," ats, pp.360-365, 14th Asian Test Symposium (ATS'05), 2005
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