14th Asian Test Symposium (ATS'05)
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
Kazuko Kambe, Nara Institute of Science and Technology, Kansai Science City , Japan
Michiko Inoue, Nara Institute of Science and Technology, Kansai Science City , Japan
Hideo Fujiwara, Nara Institute of Science and Technology, Kansai Science City , Japan
This paper presents efficient method to extract constraints from a test program template and synthesize a test program using constraint circuits. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and observation of test responses for a module under test (MUT). The constraint circuit represents a relation between operand values and inputs/output of the MUT, therefore it enables to obtain operand values using a standard automatic test pattern generator. Experimental results show that the proposed method generates accurate and compact constraint circuits, and we obtain high fault efficiency.
Citation:
Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki, "Efficient Constraint Extraction for Template-Based Processor Self-Test Generation," ats, pp.444-449, 14th Asian Test Symposium (ATS'05), 2005