Growing test costs impact the design and implementation of large and complex IP (intellectual property) modules, (often reused as embedded cores), as well as the construction of SOCs (systems-on-chip) using them. The modules must be designed for re-use in different devices, and the SOCs using them too must be designed to support various end applications, with diverse requirements of performance, power, reliability and cost, within the constraints of the budgetted design and test costs and product development cycle times. These constraints often make the DFT (design for testability) process a very critical and differentiating component of the overall design cycle, as well as a key enabler for robust designs.