Current assertion-based verification frameworks provide utilities to define assertions which are exercised during simulation. The traditional verification bottleneck of test generation, simulation, debug, and coverage analysis has been shifted but not eliminated. Defining assertions, ensuring their completeness and accuracy and maintaining a large number of assertions has proven to be the new verification bottleneck. We present a system for automatic assertion generation based on the blocklevel structural analysis of the design description. For each class of design HDL constructs, a verification assertion schema is instantiated into the design description. The system can also analyze existing assertions and identify missing or inconsistent ones. Users can select assertion schemas from the library or define new schema for a project. The resulting assertions are optimized for the target verification environment. A prototype of the system called SocVer has been developed for System-on-a-Chip interface and interconnect assertion generation and optimization.